Electronic timing device



1.. E. FLORY Oct. 29, 1946.

ELECTRONIC TIMING DEVICE 1942 2 Sheets-Sheet l lllu All 7111' F1 led Nov. 26,

:nwentor Qttorncg Oct. 29, 1946. L. E. FLORY ELECTRONIC TIMING DEVICE 2 Sheets-Sheet 2 Filed Nov. 26, 1942 l I I l attorney Patented Oct. 29, 1946 ELECTRONIC TIMING DEVICE Leslie E. Flory, Princeton. N. 1., asslgnor to Radio Corporation of America, a corporation of Delaware Application November 26, 1942, Serial No. 461,032

'lClalma.

This invention relates generally to timing devices and particularly to electronic timing devices of a type which utilizes cascaded thermionic tube trigger circuits operating from a source substantially constant frequency alternating potential.

The basic circuit utilized in adapting the invention herein to the various circuits to be described is the well known "trigger" circuitof the general type described in Theory and Application of Vacuum Tubes" by Herbert J. Reich. In one of its simplest forms, this trigger circuit includes two triodes in which the grid of the first triode is coupled to the anode of the second trlode through a network comprising a parallel connected resistor and capacitor, and the grid of the second triode is similarly coupled to the anode of the first triode through a similar coupling network. The cathodes of both triodes are grounded.

either directly, or through suitable cathode resistors. Grid and anode potentials are applied to the respective electrodes through separate resistors. If desired, a gaseous discharge tube may be connected across one of the anode resistors to indicate circuit operation.

In operation, if a negative voltage is applied to the grid of the first triode, the anode current of the triode will be reduced, and the anode potential will become more positive. Due to the connection through the coupling resistor. the grid potential of the second triode will become more positive, causing an increase in the anode current of the second triode, with a resultant decrease in the second triode anode potential. This decrease in anode potential will in turn; cause the grid potential of the first triode to become more negative. This action will continue until the anode current of the first triode is cut off. The first triode will remain cut oil, and the second triode will remain conducting, until a positive potential is applied to the grid of the first triode or until a negative potential is applied to the grid of the second triode. In either latter instance, the tube operating conditions will be reversed andthe first triode will become conducting and the anode current of the second triode will be cut oil.

One of the features of the instant invention is the utilization of such trigger circuits in cascade arrangement, whereby a predetermined change in the polarization or activization of one triode of the trigger circuit will generate a pulse to trigger or activate a succeeding trigger circuit in the cascade arrangement. As many trigger circuits as desired may be connected in cascade.

The binary system of computation is particularly suited to electronic computers since a complete binary term of abinary number may be expressed in terms of the conducting or cut-oi! condition of the anode circuit of a conventional vacuum tube. A saving in the number of tubes required for a given number is also possible in a ratio of 3 to 1 over the scale of 10 system. More complete discussions of the binary and similar systems of computation may be found in Elementary Number Theory" by Uspenskl and Heaslet, "Mathematical Excursions by H. A. Merrill, and "A Mathematician Explains" by M, I. Logston.

In order to operate a counter utilizing the binary system, it is necessary to adapt the above described trigger circuit to eilect a reversal in D0- larization or activization by succeeding mplied pulses of a similar nature. The circuits, hereinafter described, are adapted to this p se by applying in a symmetrical manner negative operating pulses to the anode circuits of the trigger tubes.

The instant invention is an improvement upon the copending application of George A. Morton and Leslie E. Flory, Ser. No. 464,292, filed November 2, 1942, entitled "Electronic Computing Devices." This copending application describes a simple counter utilizing a plurality of cascaded thermionic tube trigger circuits of the general type described heretofore in which carryover pulses are transmitted from each trigger circuit to a symmetrical common point in the anode circuits of the next succeeding trigger circuits. The operation of such a carryover system is described in detail in the copending application of George A, Morton and Leslie E. Flory, Ser. No. 464,293, filed November 2, 1942.

The present invention differs from the said copending applications in that an electronic counter in the scale of 64 is adapted to count pulses in the scale of by means of a novel feedback arrangement. A pulse counter in the scale of 64 may be provided by cascading seven thermionic trigger circuits by means of capacitors coupling the output of one tube of each trigger circuit to a common symmetrical point in the anode circuit of the next succeeding trigger circuit. In order to change the counter from the scale of 64 to the scale of 60, a second capacitor may be connected between the output of one of the tiibes of the last cascaded trigger circuit back to the symmetrical common point in theanode circuit of the third cascaded trigger circuit. This arrangement will provide 'a-pulse which effectively impresses a count of 4 upon the trigger cir. cuit each time the final count of 64 is recorded upon the last cascaded trigger circuit. It will therefore be understood that 64 pulses will be required to fill the counter on the first operation, but that only 60 will be required thereafter, This incidental error may be compensated by applying 64 pulses to the circuit prior to using it for counting purposes, or by subtracting iour pulses from the final count. It should be understood that feedback pulses may be impressed on more than one intermediate trigger circuit. For example, if the line frequency is 50 cycles, feedback pulses correspondingtoiL4and2wouldberequiredto derive one pulse persecond from acounterinthe scale of I.

A clock may be constructed utilizing a counter in the scale of 60 of the type described heretofore for converting 60 cycle line currents into one pulse per second. The single pulse per second may be applied to a second counter in the scale of 60 to derive one pulse per minute. The one pulse per minute may be applied to a third counter comprising 60 cascaded tri ger circuits, which includes a gas discharge tube or other indicator in the anode circuit of one tube of each of the trigger circuits. As explained in the copending applicat'ons. gas discharge tubes may be utilized as indicators to indicate the minute count. One pulse per hour will be derived from the minute counter and may be applied to a fourth, or hour, counter which includes twelve cascaded trigger circuits of theme general type.

Among the objects of the invention are to provide an improved method of and means for counting voltage pulses. Another object of the inventon is to provide a new and improved method of and means for providing an electronic timing circuit for operation from a source of constant frequency potentials. Another object is to provide an improved method of and means for utilizing groups of cascaded thermionic tu'be trigger circuits for counting voltage pulses and indicating the count in terms of time. Still another object of the invention is to provide a new and improved method of and means for counting voltage pulses in which cascaded trigger circuits which normally provide a counter in the scale of 64 are converted to provide a counter in the scale of 60 by means of a novel feedback arrangement. Still another object of the invention is to provide an improved method of and means for counting voltage pulses wherein the count is terminated when it attains a predetermined value. Another object of the invention is to provide an improved method of and means for cascading two groups of thermionic trigger circuits wherein voltage pulses are applied to a counter having a first predetermined numerical scale, the count is then converted to a second numerical scale, the resultant count is applied to the second group of trigger circuits which form a. counter in a third numerical scale, and the final count is converted to a fourth numerical scale.

The invention will be described by reference to the accompanying drawings of which Figure l is a schematic circuit diagram of two cascaded counters, each in a scale 64 including feedback means for converting the scale of each counter to the scale of 60; Figure 2 is a schematic circuit diagram of a portion of an electronic counter in the scale of 60; figure 3 is a schematic circuit diagram of a portion of an electronic counter in the scale of 1 and Figures 4 and 5 are schematic diagrams of typical indicators for adapting the counter circuits herein for use as an electronic clock,

Referring to the drawings, Figure 1 includes a first amplifier tube I. A standard 60 cycle line potential is applied to the control electrode of the amplifier l. The output of the first amplifier I is applied to the second amplifier tube 2 which distort the conventional wave form of the 60 cycle potential to approximately square wave form. The output of the second amplifier tube 2 is applied through a coupling capacitor 3 to the symmetrical point I of the anode circuit of a first thermionic trigger circuit I of the type described in detail heretofore. A second coupling capacitor =5 is connected between the anode of the secon tube of the first trigger circuit I and the symmetrical point 6 of the anode circuits of a second trigger circuit II. Third, fourth, fifth,

and sixth trigger circuits III, IV, V, and VI are connected respectively in cascade in the same manner to form-a counter in the-scale of 64. The carryover pulse from the anode circuit of the second tube of trigger circuit VI is applied to the control electrode-of the first tube of a. seventh trigger circuit VII. A third coupling capacitor 1 is connected between the anode of the first tube of the seventh trigger circuit VII and the symmetrical point in the anode circuit of the third trigger circuit III whereby a pulse is fed back to the third trigger circuit III each time the counter is filled. It will therefor be understood that after the counter is once filled, only sixty pulses will be required to fill the counter thereafter.

Output pulses at the rate of one per second are derived from the anode circuit of the second tube of the sixth trigger circuit VI, and applied through a. fourth coupling capacitor 8 to the symmetrical point 9 of the anode circuits of an eighth trigger circuit VIII. Additional trigger circuits IX, X, XI, X11, and XIII, are connected in cascade to trigger circuit VIII in the same manner as described heretofore for the trigger circuits I, II, III, IV, V, and VI, inclusive. The carryover pulse from the anode of the second tube of trigger circuit XIII is applied to the control electrode of the first tube of a fourteenth trigger circuit XIV. Similarly, feedback pulses are applied through a fifth coupling capacitor [2 from the anode of the first tube of trigger circuit XIV to the symmetrical point III of the anode circuits of the trigger circuit X. Pulses at the rate of one per minute are derived from the anode circuit of the second tube of trigger circuit XIII through an output coupling capacitor I I, which is connected thereto.

The seventh and fourteenth trigger circuits VII and XIV are arranged to clear automatically after each actuation thereof. These trigger circuits are of the slideback type, wherein a. pulse applied to the grid of the first tube changes the polarization of the circuit for a predetermined interval, after which it returns to its one normal or stable condition. The return of the circuit to its stable condition provides a negative feedback pulse to the preceding counter which pulse has said predetermined delay, so as to prevent coincidence with the counted pulse.

The minute pulses are then applied to the control electrode circuit, see Fig. 2, of a third amplifier tube It, the output of which is connected through a coupling capacitor I3 to the control electrode of the second tube of the first trigger circuit XX of a minute counter which includes trigger circuits connected in cascade in the manner described in the copending application of George A. Morton and Leslie E. Flory, Ser. No. 459,404, filed September 23, 1942, entitled Electronic computing devices." For purpose of illustration, only three trigger circuits are shown. Indicator lamps M which may be in the form of ga discharge tubes, are connected across the anode resistors of the second tube of each of the sixty cascaded trigger circuits which comprise the minute counter.

Pulses at the rate of one per hour are derived from the anode circuit of the second tube of the 60th trigger circuit of the minute counter, and applied to the input of a fourth amplifier tube I5, see Fig. 3, through a sixth coupling capacitor l4. The output of the fourth amplifier tube [5 is applied to the control electrode of the second tube of a first trigger circuit XXX of the hour counter which includes twelve trigger circuits connected in cascade in the same manner as described for the sixty trigger circuits of the minute counter. Only three of these trigger circuits are shown in Fig. 3. Indicator lamps 20, 2|, 22 are provided for each of the trigger circuits of the hour counter.

In the particular circuit arrangement illustrated in Figure 3, potentials are derived from the grid circuit of the second tube of each of the trigger circuits and applied to the control electrode of fifth, sixth and seventh amplifier tubes I1, l8 and I9, respectively. The output potentials derived therefrom are then applied to actuate the indicator lamps 20, 2| and 22, respectively. The amplifiers provide the necessary additional power required for actuation of high power or supplementary indicators, as for example, in a remotely operated clock circuit. It should be understood that the indicators may be operated in any other well known manner, and that, as illustrated, one amplifier and one indicator lamp will be required for each of the trigger circuits of the hour counter.

Figure 4 is one arrangement of an electronic clock face wherein small gas discharge tubes M are arranged in a single straight line to indicate minutes and a parallel row of larger gas discharge tubes H is disposed adjacent the first row of lamps to indicate hours. In the particular arrangement illustrated, the minutes read from one to sixty, reading from left to right, and the hour scale reads from 7 to 12 and l to 6, reading from left to right.

Figure 5 is a more conventional arrangement of an electronic clock face, wherein the sixty minute indicators are arranged in the form of .a circle, while the twelve hour indicators are arranged in the form of a concentric circle of greater diameter than the circle of minute indicators. It should be understood that the seconds may also be indicated by means of an additional group of sixty indicator lamps, or by means of a single indicator lamp which flashes once per second.

The clock described may be utilized for energizing any selected load circuit at predetermined time intervals. For example, it may be desirable to provide an arrangement which will operate in one hour, thirteen minutes, fifteen seconds, and twelve cycles. This may be accomplished by connecting relays in any well known manner to energize the load when the particular combination of trigger circuit conditions coincide with the selected time interval. It should be understood that various other arrangements for measuring and selecting time intervals may be utilized.

The various counters may be reset in any known manner. For example, the linear counters in the scales of 12 and 60 may be reset in the manner described in copending U. 8. application, Serial No. 459,404. The binary counters in the scales of 64, which include feedback means for converting them to the scale of 60, may be reset in the same general manner described in copending U. S. application, Serial No. 464,292. It should be understood that reset bias potentials may be applied in various other ways suggested by the copending applications described heretofore.

I claim as my invention:

1. A device including a plurality of trigger circuit units, means connecting said units in cascade with one another for establishing one cycle of operation which is completed in response to a predetermined number of impulses applied to one of said units, and means interconnecting a part of said units in a closed circuit for establishing another cycle of operation which is completed in response to a different number of said impulses.

2. A device including a plurality of trigger circuit units, means connecting said units in cascade with one another for establishing one cycle of operation which is completed in response to a predetermined number of constant frequency impulses applied to one of said units, and means including a slide-back trigger circuit unit interconnecting a part of said units in a closed circuit for establishing another cycle of operation which is completed in response to a different number of said impulses.

3. The combination of six trigger circuit units, means connecting said units in cascade for establishing one cycle of operation which is completed in response to sixty-four impulses applied to one of said units, and means interconnecting a part of said units in a closed circuit for establishing another cycle of operation which is completed in response to sixty of said impulses.

4. A device including a plurality of trigger circuit units, means connecting said units in cascade with one another for establishing one cycle of operation which is completed in response to a predetermined number of constant frequency impulses applied to one of said units, and time delay means interconnecting a part of said units in a closed circuit for establishing another cycle of operation which is completed in response to a different number of said impulses.

5. A timing device including a first group of six trigger circuit units provided with means connecting part of said units in a closed circuit to deliver a first output pulse in response to sixty input pulses, a second group of similar trigger circuit units for delivering a second output impulse in response to sixty of said first output pulses, a third group of sixty trigger circuit units interconnected to deliver a third output pulse in response to sixty of said second output pulses, and a fourth group of twelve trigger circuit units interconnected to indicate a fourth output impulse in response to twelve of said third output impulses, and means for indicating said second and said third output pulses.

6. A timing device including a first group of six trigger circuit units provided with time delay means connecting a part of said units in a closed circuit to deliver one output pulse in response to sixty input pulses, and means for establishing a representation of the number of said output pulses.

7. A timing device including a first group 01' six trigger circuit units provided with time delay means connecting a part of said units in a closed circuit to deliver one output pulse in response to sixty input pulses, and means including additional trigger circuit units for establishing a representation or the number of said output pulses.

LESLIE E. FLORY. 

